The present invention relates to a memory system of the type preferably implemented on a semiconductor chip with an electronic calculator or microprocessor system. More specifically, the invention relates to a novel scheme for inputting data to and outputting data from an array of transistor memory cells. The array of transistor memory cells are preferably implemented as a sequentially addressed memory (SAM) of the type disclosed in U.S. Pat. No. 3,893,088, "Random Access Memory Shift Register System" granted on July 1, 1975 to Anthony G. Bell and assigned to the assignee of this invention. In the prior art, it was known, to use a single commutator in a SAM and also to input or output words of numeric data to or from the registers by using a plurality of register selector gates. A plurality of control lines were used to enable the register selector gates interconnecting the register addressed with a data bus. It has been found that as the number of registers for storing numeric data increase, the number of control lines also increase; further, as the number of control lines increase, the semiconductor chip area required to implement the memory system increase at even a faster rate. Exemplary of a prior art memory system using a plurality of control lines to control the plurality of register selector gates is the SAM depicted in FIG. 8c in U.S. Pat. No. 3,924,110 "Calculator System Featuring a Subroutine Register" issued to Michael J. Cochran and Charles P. Grant, Jr. on Dec. 2, 1975 and assigned to the assignee of this invention. By using a second commutator, it has been found that the number of control lines is reduced, resulting in a net savings in silicon area.
It is therefore, one object of this invention to provide a memory system requiring less silicon area than memory systems known in the prior art. It is another object of this invention to provide a sequentially addressed memory system having two commutator systems for loading data into the memory and for reading data out of the memory.
The foregoing objects are achieved as is now described. In a preferred embodiment of the invention, an array of transistor memory cells comprising a sequentially addressed memory is implemented on a semiconductor chip. Two commutator systems are provided to access the array. A first commutator system is provided for supplying successive enabling signals to the row conductors in the sequentially addressed memory. A second commutator system is provided to successively connect the column conductors of the array with an input/output data bus. The second commutator system is preferably implemented as a shift register for controlling gates interconnecting the data bus with the column conductors of the array. In a further aspect, the first and second commutators are clocked at the same frequency; however, control means is provided to adjust the phase relationship between the first second commutators thereby providing a plurality of register storage locations within the array. A single register occupies essentially a diagonal pattern of the cells through the array. The control circuit is preferably responsive to an address indicating which one of the plurality registers implemented in the array is being addressed.